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High Speed Energy Efficient Multiplier For Digital Signal Processing

R. Muthammal1 , K. Abinaya2 , R. Aishwarya3 , D.R. Anisha4

  1. Electronics and Communication Engineering, Saveetha Engineering College (Anna University), Chennai, India.
  2. Electronics and Communication Engineering, Saveetha Engineering College (Anna University), Chennai, India.
  3. Electronics and Communication Engineering, Saveetha Engineering College (Anna University), Chennai, India.
  4. Electronics and Communication Engineering, Saveetha Engineering College (Anna University), Chennai, India.

Correspondence should be addressed to: aishumadhu9896@gmail.com, .


Section:Research Paper, Product Type: Isroset-Journal
Vol.4 , Issue.4 , pp.1-4, Apr-2018


CrossRef-DOI:   https://doi.org/10.26438/ijsrms/v4i4.14


Online published on Apr 30, 2018


Copyright © R. Muthammal, K. Abinaya, R. Aishwarya, D.R. Anisha . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
 

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IEEE Style Citation: R. Muthammal, K. Abinaya, R. Aishwarya, D.R. Anisha, “High Speed Energy Efficient Multiplier For Digital Signal Processing,” International Journal of Scientific Research in Multidisciplinary Studies , Vol.4, Issue.4, pp.1-4, 2018.

MLA Style Citation: R. Muthammal, K. Abinaya, R. Aishwarya, D.R. Anisha "High Speed Energy Efficient Multiplier For Digital Signal Processing." International Journal of Scientific Research in Multidisciplinary Studies 4.4 (2018): 1-4.

APA Style Citation: R. Muthammal, K. Abinaya, R. Aishwarya, D.R. Anisha, (2018). High Speed Energy Efficient Multiplier For Digital Signal Processing. International Journal of Scientific Research in Multidisciplinary Studies , 4(4), 1-4.

BibTex Style Citation:
@article{Muthammal_2018,
author = { R. Muthammal, K. Abinaya, R. Aishwarya, D.R. Anisha},
title = {High Speed Energy Efficient Multiplier For Digital Signal Processing},
journal = {International Journal of Scientific Research in Multidisciplinary Studies },
issue_date = {4 2018},
volume = {4},
Issue = {4},
month = {4},
year = {2018},
issn = {2347-2693},
pages = {1-4},
url = {https://www.isroset.org/journal/IJSRMS/full_paper_view.php?paper_id=582},
doi = {https://doi.org/10.26438/ijcse/v4i4.14}
publisher = {IJCSE, Indore, INDIA},
}

RIS Style Citation:
TY - JOUR
DO = {https://doi.org/10.26438/ijcse/v4i4.14}
UR - https://www.isroset.org/journal/IJSRMS/full_paper_view.php?paper_id=582
TI - High Speed Energy Efficient Multiplier For Digital Signal Processing
T2 - International Journal of Scientific Research in Multidisciplinary Studies
AU - R. Muthammal, K. Abinaya, R. Aishwarya, D.R. Anisha
PY - 2018
DA - 2018/04/30
PB - IJCSE, Indore, INDIA
SP - 1-4
IS - 4
VL - 4
SN - 2347-2693
ER -

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Abstract :
In this project, we designed an approximate 16-bit multiplier that is high speed and energy efficient. The approach is to round the operand to nearest exponent to improve the energy efficiency. Therefore, the computational intensive part of the multiplication is omitted by improving speed, area and energy consumption with small error. It is applicable to both signed and unsigned multiplications. It includes three implementation such as rounding part, signed and unsigned part. Efficiency of the multiplier is evaluated by comparing them with prior 8-bit approximate multiplier and accurate multiplier. They were also studied using the different parameters like area, power and overall efficiency. The efficiency of the multiplier can be improved and is also studied in various image processing applications. Some of the applications can be stated as image sharpening, image smoothening and image enhancement.

Key-Words / Index Term :
Compressor, energy efficiency, area efficiency, image sharpening

References :
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[3] C.H. Chang and R. K. Satzoda, December 2010, “A low error and high performance multiplexer-based truncated multiplier,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 12, pp. 1767–1771.
[4] P. Kulkarni, P. Gupta, and M. Ercegovac, January 2011 “Trading accuracy for power with an under designed multiplier architecture,” in Proc.24th IEEE Int. Conf. VLSI Design (VLSID), pp. 346–351.
[5] R. Venkatesan, A. Agarwal, K. Roy, and A. Raghunathan, “MACACO: Modeling and analysis of circuits for approximate computing,” in Proc. Int. Conf. Compute.-Aided Design, Nov. 2011, pp. 667–673.
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[7] V. Gupta, D. Mohapatra, A.Raghunathan, and K. Roy, “Low-power digital signal processing using approximate adders,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 32, no. 1, pp. 124–137, Jan. 2013.
[8] F. Farshchi, M. S. Abrishami, and S. M. Fakhraie, “New approximate multiplier for low power digital signal pocessing,” in Proc. 17th Int. Symp. Comput. Archit. Digit. Syst. (CADS), Oct. 2013, pp. 25–30.
[9] A.Kishore Kumar, D. Somasundareswari, V. Duraisamy and T. ShunbagaPradeepa, February 2013 , “Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL” Hindawi Publishing Corporation,VLSI Design, Volume 2013, pp. 1-9.

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