A 1.8V 10 bits ADC with a 8- stage pipeline and a 2 bits flash ADC with background calibration and digital correction

Sushil Bakhtar¹ , S. S. Dalu²

Section:Survey Paper, Product Type: Journal-Paper
Vol.8 , Issue.1 , pp.117-119, Feb-2020

Online published on Feb 28, 2020

Copyright © Sushil Bakhtar, S. S. Dalu . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
 

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Abstract :
This paper describes 10 bits low power pipeline analog to digital convertor with background calibration and digital correction. The 10-bit pipelined ADC is designed in a 45nm CMOS process consumes 2.350 mW with a 1.8V supply. The proposed ADC achieves low power, high resolution and high speed operation which consists of 8-stage-pipelined low resolution ADCs and a 2-bit flash ADC. Several critical technologies are used to guarantee the resolution and high sampling rate such as 1.5 bits per stage conversion, digital correction logic, folded-cascode amplifiers.

Key-Words / Index Term :
Pipeline ADC, 10 bit, low power

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