Analysis of Full and Half Adder Using Different Logic Style

Anil Pratap¹

Section:Research Paper, Product Type: Isroset-Journal
Vol.4 , Issue.1 , pp.6-9, Feb-2016

Online published on Apr 01, 2016

Copyright © Anil Pratap . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
 

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Abstract :
In recent year, power dissipation is one of the biggest challenges in VLSI design. Adder circuits are the main sources of power dissipation in signal processing units. By reducing the number of transistors in the circuits and the design structures are may occupied small area and low power design. In this paper a Full Adder Circuit is designed by using CMOS, Transmission gates and pass Transistor logic and the power and delay are analysed. Power consumption and speed are two important but conflicting design aspects; hence a better way to evaluate circuit performance is power delay product (PDP). The designs are implemented and power, delay results are obtained by using TANNER EDA Tool. The results show that the transistor counts, delay and the power required are significantly concentrated in the design.

Key-Words / Index Term :
Full Adder, CMOS, Transmission Gate (TG), Pass Transistor, Power Dissipation, Delay, PDP

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