Metastability Analysis of Synchronizer

Ankush S. Patharkar¹ , V. E. Khetade²

Section:Research Paper, Product Type: Isroset-Journal
Vol.1 , Issue.3 , pp.43-47, May-2013

Online published on Jul 07, 2013

Copyright © Ankush S. Patharkar , V. E. Khetade . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
 

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Abstract :
The multiple clock domain systems communicate with each other causes data loss. This data loss is due to mismatch in frequencies. For proper communication the frequencies must be synchronized. Hence synchronizer is used for data synchronization process with non-zero probability of failure. The synchronizer is also having its parameters. It suffers from metastability as data changes in between timing window due to which synchronizer failure occurs. As the metastability occurs we cannot predict the correct level at output. The proposed architecture is modeled with verilog and simulated with Xilinx ISE design suit 13.1and its parameter are verified with Quartus II 10.1. Analog behavior is studied by using Tanner. The probability of occurrence of metastability reduces with timing window width.

Key-Words / Index Term :
Data Synchronization, Data Loss, Synchronizer, Metastability

References :
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