Low Power Programmable Truncated Multiplier Using Error Tolerant Adder

N. Hemalatha¹ , K. Kavitha²

Section:Research Paper, Product Type: Isroset-Journal
Vol.4 , Issue.10 , pp.18-24, Oct-2018

Online published on Oct 31, 2018

Copyright © N. Hemalatha, K. Kavitha . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
 

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Abstract :
In VLSI design and testing using CMOS technology a novel error-tolerant adder (ETA) is proposed. The novel ETA is able to achieve the accuracy, and at the same time achieve more improvements in both performance of power consumption and speed. The proposed truncated multiplication reduces part of the power required by multipliers and by only computing the product of the most-significant bits. A novel approach to truncation using ETA is proposed, where a full precision multiplier is implemented. When compared to its conventional counterparts, the proposed ETA is able to attain more than 65% improvement in the Power-Delay Product (PDP). One important dynamic application of the proposed ETA is in digital signal processing systems that can tolerate particular amount of errors.

Key-Words / Index Term :
Adders, low-power design, Modified Baugh Wooley Algorithm, truncated multiplication.

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